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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Description
The MI-MV13 is a 1,280H x 1,024V (1.3 megapixel) CMOS digital image sensor capable of 500 frames-persecond (fps) operation. Its TrueSNAPTM electronic shutter allows simultaneous exposure of the entire pixel array. Available in color or monochrome, the sensor has on-chip 10-bit analog-to-digital converters (ADCs), which are self-calibrating, and a fully digital interface. The chip's input clock rate is 66 MHz at approximately 500 fps, providing compatibility with many off-the-shelf interface components. The sensor has ten 10-bit-wide digital output ports. Its open architecture design provides access to internal operations. ADC timing and pixel-read control are integrated on-chip. At 60 fps, the sensor dissipates less than 150mW, and at 500 fps less than 500mW; it operates on a 3.3V supply. Pixel size is 12 microns square, and digital responsivity is 1,600 bits per lux-second.
MT9M413
Micron Part Number: MT9M413C36STC
Features/Top Level Specifications
* Array Format: 1,280H x 1,024 V (1,310,720 pixels) * Pixel Size and Type: 12.0m x 12.0m TrueSNAP (shuttered-node active pixel) * Sensor Imaging Area: H: 15.36mm, V: 12.29mm, Diagonal: 19.67mm * Frame Rate: 0-500+ fps @ (1,280 x 1,024), >10,000 fps with partial scan, [e.g. 0-4000 fps @ (1,280 x 128)] * Output Data Rate: 660 Mbs (master clock 66 MHz, ~500 fps) * Power Consumption: < 500 mW @ 500 fps; <150 mW @ 60 fps * Digital Responsivity: Monochrome: 1,600 bits per lux-second @ 550nm; ADC reference @ 1V * Internal Intra-Scene Dynamic Range: 59dB * Supply Voltage: +3.3V * Operating Temperature: -5C to +60C * Output: 10-bit digital through 10 parallel ports * Conversion Gain = 13V/e* * * * * * * Color: Monochrome or color RGB Shutter: TrueSNAP freeze-frame electronic shutter Shutter Efficiency: >99.9% Shutter Exposure Time: 2s to > 33 msec ADC: On-chip, 10-bit column-parallel Package: 280-pin ceramic PGA Programmable Controls: Open architecture On-chip: *ADC controls *Output multiplexing *ADC calibration Off-chip: *Window size and location *Frame rate and data rate *Shutter exposure time (integration time) *ADC reference
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(c)2004 Micron Technology, Inc. All rights reserved.
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
General
The MI-MV13 is a 1280H x 1024V (1.31 megapixel) CMOS digital image sensor capable of 500 frames-persecond (fps) operation. Its TrueSNAPTM electronic shutter allows simultaneous exposure of the entire pixel array. Available in color or monochrome, the sensor has on-chip 10-bit analog-to-digital converters (ADCs), which are self-calibrating, and a fully digital interface. The chip's input clock rate is 66 MHz at approximately 500 fps, providing compatibility with many off-the-shelf interface components as shown in Figure 1. The sensor has ten (10) 10-bit-wide digital output ports. Its open architecture design provides access to internal operations. ADC timing and pixel-read control are integrated on-chip. At 60 fps, the sensor dissipates less than 150 mW, and at 500 fps less than 500 mW; it operates on a 3.3V supply. Pixel size is 12 microns square and digital responsivity is 1600 bits per lux-second. The MI-MV13 CMOS image sensor has an open architecture to provide access to its internal operations. A complete camera system can be built by using the chip in conjunction with the following external devices: * An FPGA/CPLD/ASIC controller, to manage the timing signals needed for sensor operation. * A 20mm diagonal lens. * Biasing circuits and bypass capacitors.
Figure 1: A Camera System Using the MI-MV13 CMOS Image Sensor
+3.3V ADC Bias
Off-Chip
Port 1 Port 2 D0~D9 D10~D19 D20~D29 D30~D39 D40~D49 D50~D59 D60~D69 D70~D79 D80~D89 D90~D99
On-Chip Control
Controller
(FPGA, CPLD, ASIC, etc.)
Control Timing
Pixel Array
(1280H x 1024V)
Memory
System Clock
Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10
ADC
System Clock
System Interface
On-Chip
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 2: Sensor Architecture (not to scale)
SENSE AMPS MEMORY
TOP ADCs
DIGITAL CONTROL PIXEL ARRAY
BOTTOM ADCs
Figure 3: Signal Path Diagram
Pixel
TX_N
Per Column Processing Pixel Memory
Bias VLN1 Bias VLP VREF2 ADC Calibration DAC 7 VREF1 VREF4
Photo Detector
PG_N
VRST_PIX
Buffer
Sample & Hold
ADC
BIAS VLN2
10
To ADC registers
Offset (VREF3-VCLAMP3)/20
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 4: Functional Block Diagram
TX_N PG_N PIXEL ARRAY
Row Decoder Row Driver
ROW
10
LogicRST Row Timing Block
S/H
RowSTRT
ADC #1
ADC #2
...
ADC #1280
RowDone
Sample
1280 x 10 SRAM ADC Register 1280 x 10 SRAM Output Register Column Decoder
Pads
10 x 10
Data Shift / Read
SRAM Read Control
Shift
Sense Amps Output Ports
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
External Control Sequence
The MI-MV13 includes on-chip timing and control circuitry to control most of the pixel, ADC, and output multiplexing operations. However, the sensor still requires a controller (FPGA, CPLD, ASIC, etc.) to guide it through the full sequence of its operation. With the TrueSNAP freeze-frame electronic shutter signal charges are integrated in all pixels in parallel. The charges are then sampled into pixel analog memories (one memory per pixel) and subsequently, row by row, are digitized and read out of the sensor. The integration of photosignal is controlled by two control signals: PG_N and TX_N. To clear pixels and start new integration, PG_N is made low. To transfer the data into pixel memory, TX_N is made low. The time difference between the two procedures is the exposure time. It should be noted that neither the PG_N or TX_N pulses clear the pixel analog memory. Pixel memory can be cleared during the previous readout (i.e., the readout process resets the pixel analog memory), or by applying PG_N and TX_N together (i.e., clearing both pixel and pixel memory at the same time). With the TrueSNAP freeze-frame electronic shutter the sensor can operate in either simultaneous or sequential mode in which it generates continuous video output. In simultaneous mode, as a series of frames are being captured, the PG_N and TX_N signals are exercised while the previous frame is being read out of the sensor. In simultaneous mode typically the end of integration occurs in the last row of the frame (row #1023) or in the last row of the window of interest. The position of the start integration is then calculated from the desired integration time. In sequential mode the PG_N and TX_N signals are exercised to control the integration time, and then digitization and readout of the frame takes place. Alternatively, the sensor can run in single frame or snapshot mode in which one image is captured. The sensor has a column-parallel ADC architecture that allows the array of 1,280 analog-to-digital converters on the chip to digitize simultaneously the analog data from an entire pixel row. The following input signals are utilized to control the conversion and readout process:
Table 1:
Conversion and Readout Process
DESCRIPTION Row Address Row Start Load shift register Data read enable INPUT BUS WIDTH 10-bit 1-bit 1-bit 1-bit
SIGNAL NAME ROW_ADDR ROW_STRT_N LD_SHFT_N DATA_READ_EN_N
The 10-bit ROW_ADDR (row address) input bus selects the pixel row to be read for each readout cycle. The ROW_STRT_N signal starts the process of reading the analog data from the pixel row, the analog-to-digital conversion, and the storage of the digital values in the ADC registers. When these actions are completed, the sensor sends a response back to the system controller using the ROW_DONE_N. Row address must be valid for the first half of the row processing time (the period between ROW_START_N and ROW_DONE_N). The MI-MV13 contains a pipeline style memory array, which is used to store the data after digitization. This memory also allows the data from the previous row conversion cycle to be read while a new conversion is taking place. The digital readout is controlled by lowering the LD_SHFT_N signal, followed by the DATA_READ_EN_N signal. LD_SHFT_N transfers the digitized data from the ADC register to the output register. DATA_READ_EN_N is used to enable the data output from the output register. A new pixel row readout and conversion cycle can be started two clock cycles after DATA_READ_EN_N is pulled low. The output register allows the reading of the digital data from the previous row to be performed at the same time as a new conversion (pipeline mode). This means that the total row time will be only that between when: (a) the ROW_STRT_N signal is applied and ROW_DONE_N is returned; and (b) LD_SHFT_N and DATA_READ_EN_N are applied plus two clock cycles. The pipelined operation means there will always be 1 row of latency at the start of sensor operation. The alternative to pipelined operation is burst data operation in which a new pixel row conversion is not initiated until after the output register is emptied (and LD_SHFT_N has been taken high). The ratio of line active and blanking times can be adjusted to easily match a variety of display and collection formats. See "Timing Diagram For One Row" on page 7.
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 5: Example 1 - Row 4 of the MI-MV13 Being Digitized
ADC Control s
Controller
ROW_ADDR
0 0 0 0 0 0 0 1 0 0
Column Parallel 10 -bit ADC 640 x 1 ROW 4
Even Columns
ROW_STRT_N LD_SHFT_N SYSCLK
Control Logic/ Decoders
PIXEL ARRAY
Odd Columns
ADC Control s
Column Parallel 10 -bit ADC 640 x 1 1. Reads the contents of pixel row specified by ROW_ADDR 2. Converts pixel row signals to digital values 3. Stores digital values in ADC register (1280 x 10 bit)
PG_N and TX_N
To start integration, the PG_N signal simultaneously resets the photodetectors for the entire pixel array. To end integration, the TX_N signal simultaneously transfers charge from photodetector to memory inside each pixel for the entire pixel array. In sequential mode the PG_N and the TX_N pulses must have a minimum duration of 64 SYSCLK cycles. In simultaneous mode the PG_N and TX_N pulses must have a duration of 64 SYSCLK cycles and be applied in the window between the 66th and 129th SYSCLK cycles. Additionally, in simultaneous mode between exposures a single SYSCLK duration pulse must be applied each row during the 130th clock cycle.
ROW_STRT_N
This signal reads the contents of the pixel row specified by ROW_ADDR, converts the pixel row signal to digital value, and stores the digital value in ADC register (1280 x 10-bit). This process is completed in 128-1291 SYSCLK cycles. Must be valid for a minimum of two clock cycles and a maximum of 100 clock cycles.
ROW_DONE_N
128-1291 SYSCLK cycles after ROW_STRT_N has been pulled low the sensor acknowledges the completion of a row read operation/digitization by sending out a low going pulse on this pin. Valid for two clock cycles. 1. In order to minimize the sensor power consumption, the row processing circuitry operates at SYSCLK/2. Therefore, depending on the user's implementation, there will be either 128 or 129 SYSCLK cycles between the start of ROW_STRT_N and ROW_DONE_N.
ROW_ADDR
The address for the pixel row to be read is input externally via this 10-bit input bus. Must be valid for at least 66 SYSCLK cycles, must be valid when ROW_STRT_N is pulled low.
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
LD_SHFT_N
This signal transfers the digitized data from the ADC register to the output register (1280 x 10-bit) and gates the power to the sense amplifiers. The first data (columns 1-10) are available for output at the third rising edge of SYSCLK after LD_SHFT_N is pulled low. May be enabled simultaneously with or after the falling edge of ROW_DONE_N. Must remain low the entire time the data is being read out.
Table 2:
Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10
Pixel Array
CLK 1 Col. 1 Col. 2 Col. 3 Col. 4 Col. 5 Col. 6 Col. 7 Col. 8 Col. 9 Col. 10 CLK 2 Col. 11 Col. 12 Col. 13 Col. 14 Col. 15 Col. 16 Col. 17 Col. 18 Col. 19 Col. 20
...
... ... ... ... ... ... ... ... ... ...
CLK128 Col. 1271 Col. 1272 Col. 1273 Col. 1274 Col. 1275 Col. 1276 Col. 1277 Col. 1278 Col. 1279 Col. 1280
DATA_READ_EN_N
This signal is used to enable the data output from the output register (1280 x 10-bit) to the ten, 10-bit output ports. May be initiated simultaneously with or after LD_SHFT_N is selected. Minimum width is one clock cycle.
Output Register
The use of an output register allows the processing of a row to be performed while the digital data from the previous operation is being read out of the sensor. A new pixel readout and conversion cycle can be started two clock cycles after DATA_READ_EN_N is pulled low.
Figure 6: Timing Diagram For One Row
01 2 67 129 131 0
SYSCLK ROW_ADDR [0:9] XXX ROW_STRT_N ROW_DONE_N LD_SHFT_N DATA_READ_EN_N 1-3 nsec SKEW DATA [0:99] PG2 PG_N PG1 TX_N
ROW VA LID
XXX
0
1
23
45 66
127
130
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 7: Frame Timing
ROW_ADDR [0:9] ROW_STRT_N ROW_DONE_N LD_ SHFT_N DATA_READ_EN_N DATA [0:99] PG_N=PG1+PG2 TX_ N
ROW1023 ROW0 ROW1 ROW N-1 ROW N ROW1021 ROW1022 ROW1023
1023
0
1
2
N
N+1
1022
1023
0
PG1
PG2
EXPOSURE TIM E (= 1023 -N rows)
READOUT (one full frame)
The MI-MV13 contains special self-calibrating circuitry that enables it to reduce its own column-wise fixed-pattern noise. This calibration process consists of connecting a calibration signal (VREF2) to each of the ADC inputs, and estimating and storing these offsets (7 bits) to subtract from subsequent samples. The Typical I/O Signal Timing (Initialization Sequence)
diagram (Figure 8) shows the timing sequence to calibrate the sensor. Calibration occurs automatically after logic reset (LRST_N) but it can also be started by the user, by pulling CAL_STRT_N low. When calibration is finished, the sensor generates the active low CAL_DONE_N. Significant ambient temperature drift may justify recalibration. See Figure 7 and Figure 8.
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 8: Typical I/O Signal Timing (Initialization Sequence)
CAL_STRT_N CAL_DONE_N SYSCLK
LRST_N CAL_DONE_N SYSCLK
CAL_STRT_N
CAL_STRT_N is a two-clock cycle-wide active-low pulse that initiates the ADC calibration sequence. The pulse must not be actuated for 1 microsecond after either power-up or removal of the sensor from a power-down state. Users may find it easiest to calibrate by means of the logic reset.
calibration sequence upon a logic reset. Completion of this sequence, in cases where it is initiated by a reset, is still with the CAL_DONE_N signal. This process is complete within 112 SYSCLK cycles of CAL_STRT_N. This process is complete within 112 SYSCLK cycles of LRST_N.
LRST_N
LRST_N is a two-clock cycle-wide active-low pulse that resets the digital logic. It puts all logic into a known state (all flip-flops are reset). This signal also initiates an ADC calibration sequence.
CAL_DONE_N
CAL_DONE_N is a two-clock cycle-wide active-low output pulse that is asserted when the ADC calibration is complete. The device will automatically initiate a
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Electronic Shutter
The MI-MV13 is intended to be operated primarily with the TrueSNAP freeze-frame electronic shutter, but is also capable of operating in Electronic Rolling Shutter (ERS) mode. With TrueSNAP the shutter can be operated to generate continuous video output (simultaneous mode or sequential mode) or capture single images (single frame mode). When considering timing for the various shutter modes it is useful to keep in mind the functionality of PG_N and TX_N. When PG_N is low, the photodetector is shorted to a reset voltage source. When high, the switch is open. When TX_N is low, the photodetector is shorted to pixel memory. When high, they are disconnected. Please refer to the switches shown in the Signal Path Diagram, Figure 3 on page 3. The memory is also reset during readout. It occurs for the selected row in the middle of the 0-66 clock interval after application of ROW_STRT_N (approximately clocks 20 through 40).
Figure 9: Typical Example of TrueSNAP Simultaneous Mode: Exposure During Readout
PG_N TX_N
ROW_ADDR
1023
n Exposure time
Readout
0
Readout
Time
Read row#0
TrueSNAP Simultaneous Mode
In simultaneous mode, as a series of frames are being captured, the PG_N and TX_N signals are exercised while the previous frame is being read out of the sensor. In simultaneous mode typically the "end of integration" occurs in the last row of the frame (row #1023) or in the last row of the window of interest. The position of the "start integration" is then calculated from the desired integration time. Please note that pixel memory is cleared during readout process (Figure 9).
TrueSNAP Sequential Mode
In sequential mode the PG_N and TX_N signals are exercised to control the integration time, and then digitization and readout of the frame takes place. Please note that pixel memory is cleared during readout process. The photodetector is reset when PG_N is low. Raising PG_N starts integration and lowering TX_N while PG_N is still high ends integration by sampling the signal into memory. There must be at least one SYSCLK cycle after returning TX_N to the high state until PG_N is lowered (Figure 10 on page 11).
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Read row#1023 Read row# 0
Read row#1023
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 10: Typical Example of TrueSNAP Sequential Mode: Exposure Following Readout
PG_N TX_N
Figure 11: Typical Example of TrueSNAP Single Frame Mode
PG_N TX_N
ROW_ADDR 1023 Exposure time Exposure time
ROW_ADDR
1023
EXPOSURE TIME "SLEEP" STATE "SLEEP" STATE
Readout 0 Read row#1023 Read row#0 Read row#0
Readout
Time
0
READOUT
TIME
READ ROW #0
TrueSNAP Single Frame
The MI-MV13 can run in single frame or snap-shot mode in which one image is captured. In single frame mode integration must be preceded with a void frame read (selecting all addresses and applying ROW_STRT_N) or PG_N and TX_N must be applied together (for a minimum of 10 SYSCLK cycles) to clear pixel and pixel memory. Holding PG_N and TX_N low resets the photodioide (PG_N) and the analog memory which is shorted to the photodiode by the TX_N switch. To start integration both TX_N and PG_N are released. To end integration and sample the signal into memory TX_N is made low again for 10 clocks minimum, up to 64 clocks (see Figure 6 on page 7). After TX_N is returned to the high state there must be a delay of >1 SYSCLK prior to lowering PG_N again to erase charge in the photodetector.
ERS Mode
This mode is enabled by pulling PG_N high and TX_N low.
Partial Scan Examples
The MI-MV13 can be partially scanned by sub-sampling rows. The user may select which rows and how many rows to include in a partial scan. For example, with a 66-megahertz clock, a row time is approximately 2 microseconds, resulting in the following possibilities: 1 row in frame: 500,000 frames per second 2 rows in frame: 250,000 frames per second 10 rows in frame: 50,000 frames per second 100 rows in frame: 5,000 frames per second 256 rows in frame: 2,000 frames per second 512 rows in frame: 1,000 frames per second 1,024 rows in frame: 500 frames per second ...etc
Table 3:
Pin Description
SIGNAL NAME DATA [99:0] FUNCTION Pixel data output bus that is ten pixels (100 bits) wide. Bit 0 is the LSB (least significant bit) of the lowest order pixel (See Table 2, Pixel Array, on page 7). In the group of ten pixels being output, bit 9 is the MSB (most significant bit).
PIN NUMBER(S)
T13 U14 V15 T14 V16
DATA0 DATA1 DATA2 DATA3 DATA4
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READ ROW #1023
Read row#1023
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 3:
T15 U16 R14 V18 P15 D14 A16 C16 E13 D15 A18 E14 B18 D17 E16 W11 U10 V11 R11 V12 W13 U12 V13 R12 V14 B11 C12 A12 B12 E11 B13 C14 D13 E12 C15 U6 V7 T8 R9 V8 U8 V9 T9 V10 R10
Pin Description (Continued)
SIGNAL NAME DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DATA32 DATA33 DATA34 DATA35 DATA36 DATA37 DATA38 DATA39 DATA40 DATA41 DATA42 DATA43 DATA44 DATA45 DATA46 DATA47 DATA48 DATA49 FUNCTION
PIN NUMBER(S)
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 3:
C8 A7 D9 E9 A8 C10 A9 D10 B10 C11 T4 R6 V3 W3 R7 W4 T6 V5 R8 V6 E6 D5 C5 D6 A3 C6 D7 A5 E8 A6 M5 P2 N3 T1 P3 U1 P4 T2 V1 R4 H5 E3 E2 D1 D3
Pin Description (Continued)
SIGNAL NAME DATA50 DATA51 DATA52 DATA53 DATA54 DATA55 DATA56 DATA57 DATA58 DATA59 DATA60 DATA61 DATA62 DATA63 DATA64 DATA65 DATA66 DATA67 DATA68 DATA69 DATA70 DATA71 DATA72 DATA73 DATA74 DATA75 DATA76 DATA77 DATA78 DATA79 DATA80 DATA81 DATA82 DATA83 DATA84 DATA85 DATA86 DATA87 DATA88 DATA89 DATA90 DATA91 DATA92 DATA93 DATA94 FUNCTION
PIN NUMBER(S)
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 3:
E4 C2 A1 F5 B2 L3 L2 F1
Pin Description (Continued)
SIGNAL NAME DATA95 DATA96 DATA97 DATA98 DATA99 CAL_DONE_N CAL_STRT_N DARK_OFF_EN_N FUNCTION
PIN NUMBER(S)
J4, N15, J16 H3, H18, T18 K2
VDD DGND LD_SHFT_N
J3
DATA_READ_EN_N
L1
LRST_N ROW_ADDR [9:0]
A two-clock cycle-wide active-low pulse that indicates the ADC has completed its calibration operation. Starts the calibration process for the ADC. This is a two- clock cyclewide active-low pulse. A low input enables common mode dark offset to all pixels. The value of the offset is defined by VREF3 and VCLAMP3. Subtracts a fixed offset pre-ADC. Signal is pulled up on-chip. Power supply for core digital circuitry. Ground for core digital circuitry. An active-low envelope signal that places the recently converted row of data into output register for out put, enables the sense amps and resets the column counter. An active-low envelope signal that enables the column counter and causes the ten 10-bit output ports to be updated with data on the rising edge of the system clock. Column counter skips data when this input is high. Global logic reset function (asynchronous). Active-low pulse. 10-bit bus (0 to 1023, bottom to top) that controls which pixel row is being processed or read out. An asychronous (unclocked) digital input. Bit 9 is the MSB.
G18 H16 H15 F18 G17 F17 E18 G15 F16 D18 L5 K4 H2
ROW_ADDR0 ROW_ADDR1 ROW_ADDR2 ROW_ADDR3 ROW_ADDR4 ROW_ADDR5 ROW_ADDR6 ROW_ADDR7 ROW_ADDR8 ROW_ADDR9 ROW_DONE_N ROW_STRT_N STANDBY_N
J5 G3
PIXEL_CLK_OUT SYSCLK
A two-cycle-wide pulse that indicates that processing of the currently addressed row has been completed. Starts ADC conversion of the pixel row (defined by the row address) content. A two-clock cycle-wide active-low pulse. A low input sets the sensor in a low power mode. (Allow 1 microsecond before calibrating, after coming out of this mode). Signal is pulled up on-chip. Data synchronous output. User may prefer to use this pin as data clock instead of SYSCLK. Clock input for entire chip. Maximum design frequency is 66 MHz (50%, 5%, duty cycle).
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 3: Pin Description (Continued)
SIGNAL NAME FUNCTION Power supply for digital pad ring.
PIN NUMBER(S)
G16, E10, C13, B4, VDD_IO B8, C7, F4, M2, B14, F15, R13, T12, B1, H4, N4, R3, T5, U5, W7, U9, U11, T16, B16 G5, D4, G4, K3, DGND_IO N5, P5, U4, T7, T10, U7, U13 K5, B15, B17, H17, D12, D11, E17, C9, D8 M4, T11,U18, B5,U15 R18, P18, K18,J18 VAA T17, N16, L17, K17, J15, R17 L15 M18 AGND VLN1 VLN2
Digital ground for pad ring.
Power supply for analog processing circuitry (column buffers, ADC, and support). Ground for analog signal processing circuitry. Bias setting for pixel source follower operating current. Impedance: 3k, 10pF. Decoupling capacitors recommended. The bias setting for the ADC is generated on-chip. A decoupling capacitor to ground is recommended. External biasing may be preferable to optimize performance. Impedance: 3k, 10pF. Bias setting voltage for the column source follower operating current. Impedance: 3k, 10pF. Decoupling capacitor recommended. ADC reference input voltage that sets the maximum input signal level (defines the level where the FF code occurs) and thus sets the size of the least significant bit (LSB) in the analog to digital conversion process. A smaller VREF1 produces a smaller LSB, which means a smaller analog signal level input is required to produce the same digital code out. Likewise, a larger VREF1 produces a larger LSB, which means a larger analog signal level input is required to produce the same digital code out. Thus the reference value can be used like a global gain adjustment (halving this voltage doubles the gain). This signal has two pin connections to minimize internal losses during high-speed operation. User voltage source must supply a transient current of 100mA at a frequency of 500 kHz with a 2% duty cycle. Decoupling capacitors to AGND of ~1F (ceramic) and 100F (electrolytic) placed as close to the package pins as possible are usually sufficient to filter out this required current transient. ADC reference used for the calibration operation. User voltage source must supply a transient current of 20mA at a frequency of 500 kHz with a 2% duty cycle. A ceramic decoupling capacitor to AGND of ~0.1F is usually sufficient to filter out this required current transient. Dark offset cancellation positive input reference, tied to the pedestal voltage to be added to the signal. Dark offset cancellation negative input reference. User voltage source must supply a transient current of 40mA at a frequency of 500 kHz with a 2% duty cycle. A ceramic decoupling capacitor to AGND of ~0.1F to 1F is usually sufficient to filter out this required current transient.
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
N17 K16, M15
VLP VREF1
P17
VREF2
M16 K15
VREF3 VCLAMP3
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 3:
R16 L4 M3 L18, P16, J17
Pin Description (Continued)
SIGNAL NAME VLP_DRV TX_N PG_N VRST_PIX FUNCTION Should be connected to AGND. This is an active low pulse that controls transfer of charge from photodetector to memory inside each pixel for entire pixel array. This is an active low pulse that resets the photodetectors and thereby starts new integration cycle. Power supply for pixel array. There is no noticeable dc power consumption by this pin (<100A). User voltage source must supply a transient current of 10mA at a frequency of 500 kHz, once a frame. Decoupling capacitors to AGND ~1F (ceramic) and 100F (electrolytic) are usually sufficient to filter out this required current transient. ADC reference input value should be 1/4 VREF1. User voltage source must supply a transient current of 100mA at a frequency of 500 kHz with a 2% duty cycle. A ceramic decoupling capacitor to AGND of ~0.1F is usually sufficient to filter out this required current transient. No connect.
PIN NUMBER(S)
L16
VREF4
E5,C3,C1, D2, E1,F2, F3, G1, H1, J2, J1, K1, M1, N1, N2, P1,R1, R2, T3, U2, R5, U3, V2, W2, W1, V4, W5, W6, W8, W9, W10,W12, W14, W15, W17, W18, V17, R15, U17, V19, W19, U19, T19, R19, P19, N18, N19, M19, M17, L19, K19, J19, H19, G19, F19, E19, D19, C19, B19, C18, E15, C17, D16, A19, A17, A15, A14, A13, A11, A10, B9, B7, B6, A4, E7, A2, C4, B3, W16, G2
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 12: Board Connections
Analog ground
Analog +3.3V
Digital 3.3V
_____ G18 _____ H16 _____ H15 _____ F18 _____ G17 _____ F17 _____ E18 _____ G15 _____ F16 _____ D18 _____ G3 _____ J3 _____ K2 ________ L3 _____ L5 ________ L2 _____ K4 ________ F1 _____ H2 ________ L1 _____ M3 ________ L4 ________ J5
ROWADDR0 ROWADDR1 ROWADDR2 ROWADDR3 ROWADDR4 ROWADDR5 ROWADDR6 ROWADDR7 ROWADDR8 ROWADDR9 SYSCLK DATA_READ_EN_N LD_SHFT_N CAL_DONE_N ROW_DONE_N CAL_STRT_N ROW_STRT_N DARK_OFF_EN_N STANDBY_N LRST_N PG_N TX PIXEL_CLK_OUT
Controller Interface
Analog +3.3V 1k
10F 0.1F 0,01F VCLAMP3
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DATA32 DATA33 DATA34 DATA35 DATA36 DATA37 DATA38 DATA39 DATA40 DATA41 DATA42 DATA43 DATA44 DATA45 DATA46 DATA47 DATA48 DATA49 DATA50 DATA51 DATA52 DATA53 DATA54 DATA55 DATA56 DATA57 DATA58 DATA59 DATA60 DATA61 DATA62 DATA63 DATA64 DATA65 DATA66 DATA67 DATA68 DATA69 DATA70 DATA71 DATA72 DATA73 DATA74 DATA75 DATA76 DATA77 DATA78 DATA79 DATA80 DATA81 DATA82 DATA83 DATA84 DATA85 DATA86 DATA87 DATA88 DATA89 DATA90 DATA91 DATA92 DATA93 DATA94 DATA95 DATA96 DATA97 DATA98 DATA99
AGND AGND AGND AGND AGND AGND
VDD VDD VDD
VAA VAA VAA VAA
Analog +3.3V 1k 10F 0.1F Analog +3.3V 1k 10F 0.1F Analog +3.3V 1k
100F 1F 0.01F
VLN1
VLP
VREF1
Analog +3.3V 1k
10F 0.1F VLN2 0.01F VREF2
0.1F
10F
VLP_DRV
Analog +3.3V 1k
1F 100F 0.01F
VRST_PIX
Analog +3.3V 1k
0.1F VREF4 10F
10F
0.1F
0.01F
G5 D4 G4 K3 N5 P5 U4 T7 T10 U7 U13 U15 K5 B15 B17 H17 D12 D11 C9 D8 M4 T11 U18 E17 B5 H3 H18 T18
DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGNC_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND DGND DGND
VREF3
T13 _____ U14 _____ V15 _____ T14 _____ V16 _____ T15 _____ U16 _____ R14 _____ V18 _____ P15 _____ D14 _____ A16 _____ C16 _____ E13 _____ D15 _____ A18 _____ E14 _____ B18 _____ D17 _____ E16 _____ W11 _____ U10 _____ V11 _____ R11 _____ V12 _____ W13 _____ U12 _____ V13 _____ R12 _____ V14 _____ B11 _____ C12 _____ A12 _____ B12 _____ E11 _____ B13 _____ C14 _____ D13 _____ E12 _____ C15 _____ U6 _____ V7 _____ T8 _____ R9 _____ V8 _____ U8 _____ V9 _____ T9 _____ V10 _____ R10 _____ C8 _____ A7 _____ D9 _____ E9 _____ A8 _____ C10 _____ A9 _____ D10 _____ B10 _____ C11 _____ T4 ______ R6 _____ V3 _____ W3 _____ R7 _____ W4 _____ T6 _____ V5 _____ R8 _____ V6 _____ E6 _____ D5 _____ C5 _____ D6 _____ A3 _____ C6 _____ D7 _____ A5 _____ E8 _____ A6 _____ M5 _____ P2 _____ N3 _____ T1 _____ P3 _____ U1 _____ P4 _____ T2 _____ V1 _____ R4 _____ H5 _____ E3 _____ E2 _____ D1 _____ D3 _____ E4 _____ C2 _____ A1 _____ F5 _____ B2 _____
Digital Ground
M2 B14 F15 R13 T12 B1 H4 N4 R3 T5 U5 W7 U9 U11 T16 G16 B16 E10 C13 B4 B8 C7 F4
R18 P18 K18 J18
J4 N15 J16
Pixel Data Output
Digital Ground
NOTE:
1. It is recommended that 0.01F and 0.1F capacitors be placed as physically close as possible to the MI-MV13's package. 2. Alternatively, the analog voltages depicted as being generated from potentiometers could be supplied from DACs. 3. The analog voltages VLN1, VLN2, VLP, and VREF4 are generated on-chip, but user may supply voltages to override the internal biases.
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T17 N16 K17 R17 L17 J15
Analog Ground
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Electrical Specifications Table 4:
SYMBOL Tplh Tphl Tsetup Thold
AC Electrical Characteristics
CHARACTERISTIC Data output propagation delay for low to high trans. Data output propagation delay for high to low trans. Setup time for input to SYSCLK Hold time for input to SYSCLK CONDITION MIN. 1 1 Vin = Vpwr or Vgnd Vpwr=Min,VOH min 3 3 TYP. 2 2 4 4 MAX. 3 3 UNIT ns ns ns ns
(Vsupply = 3.3V 0.3V)
Table 5:
SYMBOL VLP VREF1 VREF2 VREF3 VLN1 VLN2 VCLAMP3 VLP_DRV VRST_PIX VREF4 VIH VIL IIN VOH VOL Ipwr1
NOTE:
DC Electrical Characteristics
CHARACTERISTIC Bias for Column Buffers Reference for ADC Reference for ADC Calibration Dark offset Bias for pixel source follower Bias for ADC Dark offset Row driver control Pixel Array Power Reference for ADC Input High Voltage Input Low Voltage Input Leakage Current, No Pullup Resistor Output High Voltage Output Low Voltage Maximum Supply Current CONDITION MIN. 0.5 0.2 0.3 0 0.8 0.8 0 0 2.2 TYP. 1.9 1.0 0.8 0.6 1.0 1.0 0 0 2.7 0.25 MAX. 2.7 1.5 1.5 2.5 1.1 1.1 3.0 0 2.9 Vpwr+0.3 0.8 5 Vpwr-0.2 0.2 165 UNIT V V V V V V V V V V V V A V V mA
(Vsupply = 3.3V 0.3V)
Grounded
2.0 -0.3 Vin = Vpwr or Vgnd -5 Vpwr=Min, IOH=100A Vpwr=Min, IOL=100A 66 MHz clock, 5pF load on outputs
1. Ipwr = I (VDD_IO) + I (VDD) + I (VAA)
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 6:
SYMBOL Vpwr Vin Vout I I
NOTE:
Absolute Maximum Ratings
PARAMETER DC Supply Voltage DC Input Voltage DC Output Voltage DC Current Drain per Pin (Any I/O) DC Current Drain, Vpwr and Vgnd VALUE -0.5 to 3.6 -0.5 to Vpwr + 0.5 -0.5 to Vpwr + 0.5 50 100 UNIT V V V mA mA
Vpwr = VDD = VAA = VDD_IO (VDD is supply to digital circuit, VAA to analog circuit). Vgnd = DGND = AGND (DGND is the ground to the digital circuit, AGND to the analog circuit).
Table 7:
SYMBOL Vpower TA
NOTE:
Recommended Operating Conditions
PARAMETER DC Supply Voltage Commercial Operating Temperature MIN. 3.00 -5 MAX. 3.6 60 UNIT V C
This device contains circuitry to protect the inputs against damage from high static voltages or electric fields, but the user is advised to take precautions to avoid the application of any voltage higher than the maximum rated.
Table 8:
SYMBOL Pavg
Power Dissipation
PARAMETER Average Power MIN. 250 TYP. 350 MAX. 500 UNIT mW
(Vpwr = 3.3V; TA = 25C @500 fps)
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Analog Voltage Setting Considerations
The values suggested in the Typical Values column in the "AC Electrical Characteristics" on page 18 should be the starting point for setting the analog voltages. Additionally, it is useful to refer to the "Signal Path Diagram" on page 3 that indicates how the analog voltages affect the image. Other considerations are as follows: VREF1 This ADC reference voltage can also be utilized as a gain. A lower value will increase gain, but also results in amplification of nonuniformities. VREF4: Should always be set to 1/4 of VREF1. VREF2 Reference used for the ADC calibration to remove column-wise FPN. If set much lower than the typical value there is a possibility that some column nonuniformities will not be corrected. Setting higher than typical will result in more column-wise FPN. When debugging analog voltage settings it may be useful to temporarily set VREF2 to zero, effectively stopping the ADC calibration process and adjusting the VLN/VLP settings. VLN1 The on-chip generated voltage should be used as the starting point; increasing above typical will result in an increase in current, speed, and FPN in the first buffer. VLN2 The on-chip generated voltage should be used as the starting point. Controls the current in the ADC comparators (there is a safe range where this voltage has no effect); above or below this range will cause the comparators to fail. If vertical white stripes appear in the center of the imaging area or random white spots appear in contour areas, it is an indication that VLN2 needs to be adjusted. VLP The on-chip generated voltage should be used as the starting point. VRST_PIX Voltage for pixel reset. If this is too close to VAA the image will be degraded and is not recommended to be above 2.9V, but if it is set too low the pixel dynamic range may decrease. In the initial preproduction version of the MI-MV13 the number of defects increased with reduced VRST_PIX so it was recommended to keep this as high as possible. If high VRST_PIX resulted in vertical FPN it was compensated via adjustments to VLN1 and VLN2. VREF3 and VCLAMP3 These control the offset as shown in the "Signal Path Diagram" on page 3. This must be enabled via DARK_OFF_EN_N; Offset is ~ (VREF3-VCLAMP3)/20.
Figure 13: Set Up and Hold Time
SYSCLK INPUT T setup T hold
Figure 14: Clock to Data Propagation Delay tr
Tplh, Tphl
SYSCLK
DOUT (99:0)
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 15: Pixel Array Layout
(1023, 1279) Megapixel (1280H x 1024V) 1280 x 1024 active pixels (0,0) area of detail below
no black rows
Figure 16: Bayer Pattern (Pixel Color Pattern Detail)
(0,0)
G B G B G
R G R G R
G B G B G
... R G R G R G B G B G R G R G R
G B G B G
...
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Optical Specification Table 9:
TA = 25C SYMBOL I Nsat NADC DSNU, HF1 DSNU, LF2 Vdrk NE Dyn_I PRNU, HF1 PRNU, LF2 Kdrk
NOTE:
R
Image Sensor Characteristics
PARAMETER Responsivity (ADC VREF=1V) Pixel saturation level DC noise + DNL Dark signal non-uniformity, high spatial frequency Dark signal non-uniformity, low spatial frequency Output referred dark signal Input referred noise Internal dynamic range Photo response non-uniformity, high spatial frequency Photo response non-uniformity, low spatial frequency Dark current temperature coefficient TYP 1600 63,000 2 <0.4 <1.5 50 70 59 <0.6 <10 100 UNIT LSB/lux-sec. eLSB p-p % rms % p-p mV/sec edB % rms % p-p %/8C
1. Calculation method for high frequency PRNU and DSNU:
For PRNU, uniformly adjust illumination so that the average voltage across a sensor partition is Full Scale/2. For DSNU, block illumination to sensor. Integration time = 2ms. Calculate spatially-filtered average using 64 pixel square window. Calculate r.m.s. difference between pixel values and corresponding filtered average values. Calculate average r.m.s. between windows.
2. Calculation method for low frequency PRNU and DSNU:
For PRNU, uniformly adjust illumination so that the average voltage across a sensor partition is Full Scale/2. For DSNU, block illumination to sensor. Integration time = 2ms Calculate spatially-filtered average using 64 pixel square window Calculate difference between the center pixel value and corresponding filtered average values. Report peak to peak values between windows.
Table 10: Pixel Array Specifications
SYMBOL Resolution Pixel size Pixel pitch Pixel fill factor PARAMETER Number of pixels in active image X-Y dimensions Center-to-center pixel spacing Area of drawn active area TYP. 1280 x 1024 12 x 12 12 40 UNIT pixels m m %
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 17: Quantum Efficiency
Quantum Effficiency for Color
25
20
Quantum Efficiency (%
15
10
5
0 400
500
600
700
Wavelength (nm)
800
900
1000
Green 1 pixels
Green 2 pixels
Blue pixels
Red pixels
Quantum Effficiency for Monochrome
30
25
Quantum Efficiency (%
20
15
10
5
0 400
500
600
700 Wavelength (nm)
800
900
1000
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Lens Selection
Much of the specific information in this section is explained in detail at http://www.micron.com/products/imaging/technology/index.html on our web site. The following information applies specifically to the MI-MV13 megapixel image sensor. may be desired. The approximate field of view that an imaging system can achieve is shown in the following equation:
w 2 tan -1 ---- 2f
where is the field of view, tan-1 is the trigonometric function arc-tangent, w is the width of the image sensor, and f is the focal length of the imaging lens. For example, the imaging system's diagonal field of view can be determined by using the diagonal of the image sensor (19.67 mm) for w and a particular lens' focal length for f. Alternatively, the imaging system's horizontal field of view can be determined by using the horizontal of the image sensor (15.36 mm) for w and a particular lens' focal length for f. A lens with an approximately 50 mm focal length will provide an 18degree horizontal field of view with a MI-MV13 (keep in mind that the above equation is a simplified approximation).
Format
The diagonal of the image sensor array, 19.67mm, fits most closely, but not exactly, within the optical format corresponding to the 1-inch specification. Some 1-inch optical format lenses have been shown to work well with this sensor. Typical 1-inch lens examples are Computer V2513, V5013, and V7514. F-mount lenses provide another possible lens solution due to their large image circle.
Mounting
Several lens mounting standards exist that specify the threading of the lens' barrel as well as the distance the back flange of the lens should be from the image sensor for the lens to properly form an image. Typical lens mounting standards for the MI-MV13 are:
F-Number
The f-number, or f-stop, of an imaging lens is the ratio of the lens' focal length to its open aperture diameter. Every doubling in f-number reduces the light to the sensor by a factor of four. For example, a lens set at f/1.4 lets in four times more light than that same lens when it is set at f/2.8. Low f-number lenses capture a lot of light for delivery to the image sensor, but also require careful focus. Higher f-number lenses capture less light for delivery to the image sensor, and do not require as much effort to bring the imaging system to focus. Low f-number lenses generally cost more than high f-number lenses of similar overall performance. Typical f-numbers for various imaging systems are:
Table 11: Lens Mounting Standards
MOUNT NAME C CS MOUNTING THREADS 1 - 32 1 - 32 BACK-FLANGE-TO-IMAGESENSOR 17.526 mm 12.5 mm
Another option is to use a C-mount together with a C-to F-mount adapter for greater lens flexibility.
Field of View and Focal Length
The field of view of an imaging system will depend on both the focal length of the imaging lens and the width of the image sensor. As most of the image information humans pay attention to generally falls within a 45-degree horizontal field of view, many camera systems attempt to imitate this field of view. However, in some cases a telephoto system (with a narrow field of view, say less than 20 degrees), or a wide angle system (with a wide field of view, say more than 60 degrees)
Table 12: Typical F-Numbers
F-STOP 1.4 2.0 2.8 4.0+ IMAGING APPLICATION Low-light level imaging, manual focus systems Typical for PC and other small form cameras Common in digital still cameras Often used in machine vision applications
MTF
Modulation Transfer Function (MTF) is a technical term that quantifies how well a particular system propagates information. For cameras, the "system" is the
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
lens and the sensor, and the "information" is the picture they are capturing. MTF ranges from zero (no information gets through) to 100 (all information gets through), and is always specified in terms of information density. In most imaging systems, the MTF is limited by the performance of the imaging lens. A lens must be able to transfer enough information to the image sensor to be able to resolve details in the image that are as small as the pixels in the image sensor. The pixels are set on a 12-micron pitch (the center of one pixel is 12 microns from the center of its neighboring pixel). Thus, a lens used should be able to resolve image features as small as 12 microns. Typically, a lens' MTF is plotted as a function of the number of line pairs per millimeter the lens is attempting to resolve (more line pairs per millimeter mean higher information densities). For an electronic imaging system, one line pair will correspond to two image sensor pixels (each pixel can resolve one line). This is equated as: must be decided by the end user is how high the MTF needs to be for a particular imaging situation. Generally, near an image sensor's LP/mm good MTFs are higher than 40, moderate MTFs are from 20 to 40, and poor MTFs are less than 20.
Infrared Cut-Off Filters
In most visible imaging situations it is necessary to include a filter in the imaging path that blocks infrared (IR) light from reaching the image sensor. This filter is called an IR cut-off filter. Various forms of IR cut-off filters are available, some absorptive (like Hoya's CM500 or Schott's BG18) and some reflective (i.e., dielectric stacks). Infrared light poses a problem to visible imaging because its presence blurs and decreases the MTF in the images formed by a lens. Since human vision only extends across a narrow range of the electromagnetic spectrum, camera systems hoping to capture images that look like the images our eyes capture must not capture light outside of our vision range. Siliconbased light detectors (like the ones in the MI-MV13's pixels) detect light from the very deep blue to the near infrared. Thus, a filter must exist in the light's path that keeps the infrared from reaching the image sensor's pixels. In most cases, it is important that such a filter begin blocking light around 650 nm (in the deep red) and continue blocking it until at least 1100 nm (in the near IR). In most camera systems, the IR cut-off filter is included in the imaging lens. However, this point must be verified by a lens vendor when a particular lens is chosen for use with an image sensor.
LP1-------- = ---mm 2z
where LP/mm means line pairs per millimeter and z is the image sensor's pixel pitch, in millimeters. For the MI-MV13, z = 0.012 mm, such that the MI-MV13 has 42 LP/mm. Thus, a lens should provide an acceptable level of MTF all the way out to 42 LP/mm. For most lenses, the MTF will be highest in the center of the images they form, and gradually drop off toward the edges of the images they form. As well, MTFs at low values of LP/mm will generally be larger than MTFs at high values of LP/mm. One of the many trade-offs that
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 18: C-Mount Lens Shroud for MI-MV13 and Socket
Threaded holes for 4-40 screws (4 places) BASE
2.50"
0.015" Recess
0.125 0.125 2.50" 0.25"
0.25"
0.75"
LID
Holes Dia = 0.12" (for 4-40 screws), 4 places No thread
2.50"
1-32 Thread
1.25
2.50"
0.125"
0.0 0.0
NOTE:
1.25"
2.50"
0.25"
This shroud is designed to accommodate the MI-MV13 when it is inserted into a PGA socket. These dimensions are based on the MILL MAX #510-93-281-19-081003 socket (www.mill-max.com).
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 19: 280-Pin Ceramic PGA Package Top View
1.9000.018 1.3430.016 1.1060.012 1.0670.012 0.8400.009 0.8400.008
INDEX
0.003 (1023, 1279)
COLUMN
0.782
ROW
(0, 0)
19mils
0.003 0.743
Notes: 1. Sensor is centered on package, pixel array is off-center. 2. Die offset is 10 mils in both the X and Y directions. 3. Die rotation is 2 degrees.
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1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 20: 280-Pin Ceramic PGA Package Side View
0.118 0.012 0.039 0.004 0.012 0.002 0.020 0.002 (0.0235 X 2) 0.047 0.005 0.007 (AT CERAMIC)
R0.005
BRAZE
Glass Lid Die
(0.008)
UNITS: INCHES Notes: 1. Die thickness 28.5 mils 1 mil. 2. Die epoxy thickness 1 mil. 3. D-263 glass lid thickness 31 2 mils. 4. Glass lid epoxy thickness 1 mil.
0.039 0.005 0.150 0.008
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0.047 0.005 (4X)
0.0180.002 (281X)
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 21: 280-Pin Ceramic PGA Package Bottom View
1.800 0.012 (P = 0.100 X 18)
0.100 typ.
W V U T R P N
(281X) 0.067 TYP. DIA. EXTRA PIN
M L K J H G F E D C B A
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Alumina Coat
09005aef806807ca MT9M413C36STC.fm - Ver. 3.0 1/04 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
1.3-MEGAPIXEL CMOS ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Environmental Table 13: Absolute Maximum Ratings
SYMBOL Tstorage Tlead PARAMETER Storage Temperature Range Lead Temperature (10 second soldering) VALUE -40 to 125 235 max. UNIT C C
Document History Table 14: Document Change History
CHANGE Ver. 3.0 Ver. 3.0 DATE 1/7/04 CHANGED BY EJakl COMMENTS Initial release 1. Page 1, added additional bullet under Features/Top Level Specifications:
* Conversion Gain = 13V/e-
2. Page 11, added "for 10 clocks minimum, up to 64 clocks (see Figure 6, page 7)" line 12 in paragraph titled TrueSNAP Single Frame. 3. Page 15, added "(halving this voltage doubles the gain)" under FUNCTION, for Pin Numbers K16, M15. 4. Page 20, Updated Figure 13.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, the Micron logo, and TrueSNAP are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
09005aef806807ca MT9M413C36STC.fm - Ver. 3.0 1/04 EN Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
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